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33 17, 1.5 gbps digital crosspoint switch ad8150 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features low cost 33 17, fully differential, nonblocking array >1.5 gbps per port nrz data rate wide power supply range: +5 v, +3.3 v, ?3.3 v, ?5 v low power 400 ma (outputs enabled) 30 ma (outputs disabled) pecl and ecl compatible cmos/ttl-level control inputs: 3 v to 5 v low jitter: <50 ps p-p no heat sinks required drives a backplane directly programmable output current optimize termination impedance user-controlled voltage at the load minimize power dissipation individual output disable for busing and building larger arrays double row latch buffered inputs available in 184-lead lqfp applications hd and sd digital video fiber optic network switching general description ad8150 is a member of the x stream line of products and is a breakthrough in digital switching, offering a large switch array (33 17) on very little power, typically less than 1.5 w. additionally, it operates at data rates in excess of 1.5 gbps per port, making it suitable for hdtv applications. further, the pricing of the ad8150 makes it affordable enough to be used for sd applications. the ad8150 is also useful for oc-24 optical network switching. the ad8150s flexible supply voltages allow the user to operate with either pecl or ecl data levels and will operate down to 3.3 v for further power reduction. the control interface is cmos/ttl compatible (3 v to 5 v). its fully differential signal path reduces jitter and crosstalk while allowing the use of smaller single-ended voltage swings. the ad8150 is offered in a 184-lead lqfp package that operates over the industrial temperature range of 0c to 85c. functional block diagram outp outn inp inn cs re we d a update reset first rank 17 ? 7-bit latch second rank 17 ? 7-bit latch input decoders output address decoder 33 ? 17 differential switch matrix 17 17 33 33 7 5 ad8150 01074-001 figure 1. functional block diagram 100ps/div 500mv ? 500mv 100mv/ div 01074-002 figure 2. output eye pattern, 1.5 gbps
ad8150 rev. a | page 2 of 44 table of contents specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 maximum power dissipiation .................................................... 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ............................................. 9 test circuit ...................................................................................... 13 control interface............................................................................. 14 control interface truth tables ................................................. 14 control interface timing diagrams ........................................ 15 control interface programming example .............................. 20 control interface description................................................... 21 control pin description ............................................................ 21 control interface translators.................................................... 22 circuit description......................................................................... 23 high speed data inputs (inxxp, inxxn)................................ 23 high speed data outputs (outyyp, outyyn) .................... 23 output current set pin (ref).................................................. 24 power supplies ............................................................................ 25 power dissipation....................................................................... 27 heat sinking................................................................................ 28 applications..................................................................................... 29 ad8150 input and output busing........................................... 29 evaluation board ............................................................................ 30 configuration programming.................................................... 30 power supplies ............................................................................ 30 software installation .................................................................. 30 software operation .................................................................... 31 pcb layout...................................................................................... 32 outline dimensions ....................................................................... 42 ordering guide .......................................................................... 42 revision history 9/05 rev. 0 to rev. a updated format..................................................................universal change to absolute maximum ratings......................................... 4 changes to maximum power dissipation section....................... 4 change to figure 3 ........................................................................... 4 changes to figure 40...................................................................... 26 updated outline dimensions ....................................................... 42 changes to ordering guide .......................................................... 42 revision 0: initial version
ad8150 rev. a | page 3 of 44 specifications at 25c, v cc = 3.3 v to 5 v, v ee = 0 v, r l = 50 (see figure 25), i out = 16 ma, unless otherwise noted. table 1 parameter conditions min typ max unit dynamic performance max data rate/channel (nrz) 1.5 gbps channel jitter data rate < 1.5 gbps 50 ps p-p rms channel jitter v cc = 5 v 10 ps propagation delay input to output 650 ps propagation delay match 50 100 ps output rise/fall time 20% to 80% 100 ps input characteristics input voltage swing differential 200 1000 mv p-p input voltage range common mode v cc ? 2 v cc v input bias current 2 a input capacitance 2 pf input v in high v cc ? 1.2 v cc ? 0.2 v input v in low v cc ? 2.4 v cc ? 1.4 v output characteristics output voltage swing differential (see figure 25) 800 mv p-p output voltage range v cc ? 1.8 v cc v output current 5 25 ma output capacitance 2 pf power supply operating range pecl, v cc v ee = 0 v 3.3 5 v ecl, v ee v cc = 0 v ?5 ?3.3 v v dd 3 5 v v ss 0 v quiescent current v dd 2 ma v ee all outputs enabled, i out = 16 ma 400 ma t min to t max 450 ma all outputs disabled 30 ma thermal characteristics operating temperature range 0 85 c ja 30 c/w logic input characteristics v dd = 3 v dc to 5 v dc input v in high 1.9 v dd v input v in low 0 0.9 v
ad8150 rev. a | page 4 of 44 absolute maximum ratings table 2. parameter rating supply voltage v dd ? v ee 10.5 v internal power dissipation 1 ad8150 184-lead plastic lqfp (st) 4.2 w differential input voltage v cc ? v ee output short-circuit duration observe power derating curves storage temperature range 2 ?65c to +125c 1 specification is for device in free air (t a = 25c): 184-lead plastic lqfp (st): ja = 30c/w. 2 maximum reflow temperatures are to jedec industry standard j-std-020. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipiation the maximum power that can be safely dissipated by the ad8150 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 125c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 125c for an extended period can result in device failure. while the ad8150 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (125c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 3. 6 1 2 3 4 5 ?10 90 80 70 60 50 40 30 20 10 0 01074-003 ambient temperature ( c) maximum power dissipation (w) t j = 150 c figure 3. maximum power dissipation vs. temperature esd caution esd (electrostatic discharge) sensit ive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8150 rev. a | page 5 of 44 pin configuration and fu nction descriptions 184 183 182 181 180 179 178 177 176 175 174 173 171 170 169 168 167 166 165 164 163 162 172 161 160 159 157 156 155 154 153 152 158 151 150 149 147 146 145 144 143 142 141 140 139 148 59 60 61 62 63 64 65 66 67 68 47 48 49 50 51 52 53 54 55 56 57 58 69 70 71 72 74 75 76 77 78 73 79 80 81 82 84 85 86 87 83 88 89 90 91 92 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 40 39 38 37 41 43 42 45 44 46 in20p v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee a0 v ee v cc v ee in19n in19p in18n in18p in17n in17p in16n in16p reset cs re we update a0 a1 a2 a3 a4 d0 d1 d2 d3 d4 d5 d6 ref in15n in15p in14n in14p in13n in13p v ee v ee v ee v ee v ee v ss v cc v ee v ee v ee v ee v ee ref v cc v dd v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee a16 v cc in20n in21p in21n in22p in22n in23p in23n in24p in24n in25p in25n in26p in26n in27p in27n in28p in28n in29p in29n in30p in30n in31p in31n in32p in32n out16n out16p in12n in12p in11n in11p in10n in10p in09n in09p in08n in08p in07n in07p in06n in06p in05n in05p in04n in04p in03n in03p in02n in02p in01n in01p in00n in00p out00p out00n 122 137 138 132 133 134 135 130 131 129 136 127 128 123 124 125 126 120 121 118 119 116 117 113 114 115 111 112 109 110 108 105 106 107 104 102 103 100 101 95 96 97 98 99 93 94 pin 1 indicator ad8150 184l lqfp top view (not to scale) out15n out15p out14n out14p out13n out13p out12n out12p out11n out11p out10n out10p out09n out09p out08n out08p out07n out07p out06n out06p out05n out05p out04n out04p out03n out03p out02n out02p out01n out01p v ee v ee a15 v ee a14 v ee a13 v ee a12 v ee a11 v ee a10 v ee a9 v ee a8 v ee a7 v ee a6 v ee a5 v ee a4 v ee a3 v ee a2 v ee a1 01074-004 figure 4. pin configuration
ad8150 rev. a | page 6 of 44 table 3. pin function descriptions pin no. mnemonic type description 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 42, 46, 47, 92, 93, 99, 102, 105, 108, 111, 114, 117, 120, 123, 126, 129, 132, 135, 138, 139, 142, 145, 148, 172, 175, 178, 181, 184 v ee power supply most negative pecl suppl y (common with other points labeled v ee ) 2 in20p pecl high speed input 3 in20n pecl high speed input complement 5 in21p pecl high speed input 6 in21n pecl high speed input complement 8 in22p pecl high speed input 9 in22n pecl high speed input complement 11 in23p pecl high speed input 12 in23n pecl high speed input complement 14 in24p pecl high speed input 15 in24n pecl high speed input complement 17 in25p pecl high speed input 18 in25n pecl high speed input complement 20 in26p pecl high speed input 21 in26n pecl high speed input complement 23 in27p pecl high speed input 24 in27n pecl high speed input complement 26 in28p pecl high speed input 27 in28n pecl high speed input complement 29 in29p pecl high speed input 30 in29n pecl high speed input complement 32 in30p pecl high speed input 33 in30n pecl high speed input complement 35 in31p pecl high speed input 36 in31n pecl high speed input complement 38 in32p pecl high speed input 39 in32n pecl high speed input complement 41, 98, 149, 171 v cc power supply most positive pecl supply (common with other points labeled v cc ) 43 out16n pecl high speed output complement 44 out16p pecl high speed output 45 v ee a16 power supply most negative pecl supply (unique to this output) 48 out15n pecl high speed output complement 49 out15p pecl high speed output 50 v ee a15 power supply most negative pecl supply (unique to this output) 51 out14n pecl high speed output complement 52 out14p pecl high speed output 53 v ee a14 power supply most negative pecl supply (unique to this output) 54 out13n pecl high speed output complement 55 out13p pecl high speed output 56 v ee a13 power supply most negative pecl supply (unique to this output) 57 out12n pecl high speed output complement 58 out12p pecl high speed output 59 v ee a12 power supply most negative pecl supply (unique to this output) 60 out11n pecl high speed output complement 61 out11p pecl high speed output 62 v ee a11 power supply most negative pecl supply (unique to this output) 63 out10n pecl high speed output complement 64 out10p pecl high speed output
ad8150 rev. a | page 7 of 44 pin no. mnemonic type description 65 v ee a10 power supply most negative pecl supply (unique to this output) 66 out09n pecl high speed output complement 67 out09p pecl high speed output 68 v ee a9 power supply most negative pecl supply (unique to this output) 69 out08n pecl high speed output complement 70 out08p pecl high speed output 71 v ee a8 power supply most negative pecl supply (unique to this output) 72 out07n pecl high speed output complement 73 out07p pecl high speed output 74 v ee a7 power supply most negative pecl supply (unique to this output) 75 out06n pecl high speed output complement 76 out06p pecl high speed output 77 v ee a6 power supply most negative pecl supply (unique to this output) 78 out05n pecl high speed output complement 79 out05p pecl high speed output 80 v ee a5 power supply most negative pecl supply (unique to this output) 81 out04n pecl high speed output complement 82 out04p pecl high speed output 83 v ee a4 power supply most negative pecl supply (unique to this output) 84 out03n pecl high speed output complement 85 out03p pecl high speed output 86 v ee a3 power supply most negative pecl supply (unique to this output) 87 out02n pecl high speed output complement 88 out02p pecl high speed output 89 v ee a2 power supply most negative pecl supply (unique to this output) 90 out01n pecl high speed output complement 91 out01p pecl high speed output 94 v ee a1 power supply most negative pecl supply (unique to this output) 95 out00n pecl high speed output complement 96 out00p pecl high speed output 97 v ee a0 power supply most negative pecl supply (unique to this output) 100 in00p pecl high speed input 101 in00n pecl high speed input complement 103 in01p pecl high speed input 104 in01n pecl high speed input complement 106 in02p pecl high speed input 107 in02n pecl high speed input complement 109 in03p pecl high speed input 110 in03n pecl high speed input complement 112 in04p pecl high speed input 113 in04n pecl high speed input complement 115 in05p pecl high speed input 116 in05n pecl high speed input complement 118 in06p pecl high speed input 119 in06n pecl high speed input complement 121 in07p pecl high speed input 122 in07n pecl high speed input complement 124 in08p pecl high speed input 125 in08n pecl high speed input complement 127 in09p pecl high speed input 128 in09n pecl high speed input complement 130 in10p pecl high speed input
ad8150 rev. a | page 8 of 44 pin no. mnemonic type description 131 in10n pecl high speed input complement 133 in11p pecl high speed input 134 in11n pecl high speed input complement 136 in12p pecl high speed input 137 in12n pecl high speed input complement 140 in13p pecl high speed input 141 in13n pecl high speed input complement 143 in14p pecl high speed input 144 in14n pecl high speed input complement 146 in15p pecl high speed input 147 in15n pecl high speed input complement 150 v ee ref r-program connection point for output logic pull-down programming resistor (must be connected to v ee ) 151 ref r-program connection point for outp ut logic pull-down programming resistor 152 v ss power supply most negative control logic supply 153 d6 ttl enable/disable output 154 d5 ttl (32) msb input select 155 d4 ttl (16) 156 d3 ttl (8) 157 d2 ttl (4) 158 d1 ttl (2) 159 d0 ttl (1) lsb input select 160 a4 ttl (16) msb output select 161 a3 ttl (8) 162 a2 ttl (4) 163 a1 ttl (2) 164 a0 ttl (1) lsb output select 165 update ttl second-rank program 166 we ttl first-rank program 167 re ttl enable readback 168 cs ttl enable chip to accept programming 169 reset ttl disable all outputs (hi-z) 170 v dd power supply most positive control logic supply 173 in16p pecl high speed input 174 in16n pecl high speed input complement 176 in17p pecl high speed input 177 in17n pecl high speed input complement 179 in18p pecl high speed input 180 in18n pecl high speed input complement 182 in19p pecl high speed input 183 in19n pecl high speed input complement
ad8150 rev. a | page 9 of 44 typical performance characteristics rms pk-pk v oh (v) jitter (ps) 100 80 60 40 20 0 0 ?0.2 ?0.6 ?0.8 ?1.0 ?1.2 ?0.4 ?1.4 01074-005 v ee = ?3.3v (v oh ? v ol = 800mv) figure 5. jitter vs. v oh 1.5 gbps, prbs 23 rms pk-pk v in (v) jitter (ps) 100 80 60 40 20 0 ?2.0 ?1.5 ?0.5 0 ?1.0 0.5 01074-006 v ee = ?3.3v (v ih ? v il = 800mv) figure 6. jitter vs. v ih 1.5 gbps, prbs 23 rms pk-pk data rate (gbps) jitter (ps) 100 80 60 40 20 0 0.1 1.5 1.3 1.1 0.9 0.7 0.5 0.3 01074-007 v ee = ?3.3v figure 7. jitter vs. data rate, prbs 23 rms pk-pk v oh (v) jitter (ps) 100 80 60 40 20 0 0 ?0.2 ?0.6 ?0.8 ?1.0 ?1.2 ?0.4 ?1.4 01074-008 v ee = ?5v (v oh ? v ol = 800mv) figure 8. jitter vs. v oh 1.5 gbps, prbs 23 rms pk-pk v in (v) jitter (ps) 100 80 60 40 20 0 ?2.0 ?1.5 ?0.5 0 ?1.0 0.5 01074-009 v ee = ?5v (v ih ? v il = 800mv) figure 9. jitter vs. v ih 1.5 gbps, prbs 23 rms pk-pk data rate (gbps) jitter (ps) 100 80 60 40 20 0 0.1 1.5 1.3 1.1 0.9 0.7 0.5 0.3 01074-010 v ee = ?5v figure 10. jitter vs. data rate, prbs 23
ad8150 rev. a | page 10 of 44 rms pk-pk i out (ma) jitter (ps) 100 80 60 40 20 0 0 5 10 15 20 25 01074-011 v ee = ?3.3v figure 11. jitter vs. i out 1.5 gbps, prbs 23 rms pk-pk temperature ( c) jitter (ps) 100 80 60 40 20 0 ?25 0 25 50 75 125 100 01074-012 v ee = ?3.3v figure 12. jitter vs. temperature 1.5 gbps, prbs 23 time domain 2 23 ?1 pseudo-random bit stream, error-free area error-free percentage value was computed using the following formula: (data_period ? ppjitter) 100 / data_period time domain v inner 100 / v inner @500mbps voltage (inner eye) voltage (inner eye) data rate (mbps) percent 100 80 60 40 20 0 0 500 1000 1500 01074-013 v ee = ?3.3v figure 13. ac performance rms pk-pk i out (ma) jitter (ps) 100 80 60 40 20 0 0 5 10 15 20 25 01074-014 v ee = ?5v figure 14. jitter vs. i out 1.5 gbps, prbs 23 rms pk-pk temperature ( c) jitter (ps) 100 80 60 40 20 0 ?25 0 25 50 75 125 100 01074-015 v ee = ?5v figure 15. jitter vs. temperature 1.5 gbps, prbs 23 time domain 2 23 ?1 pseudo-random bit stream, error-free area error-free percentage value was computed using the following formula: (data_period ? ppjitter) 100 / data_period time domain v inner 100 / v inner @500mbps voltage (inner eye) voltage (inner eye) data rate (mbps) percent 100 80 60 40 20 0 0 500 1000 1500 01074-016 v ee = ?5v figure 16. ac performance
ad8150 rev. a | page 11 of 44 delay (ps) frequency 100 80 60 40 20 0 560 580 620 600 640 660 680 700 710 01074-017 figure 17. variation in channel-to-channel delay, all 561 points v ee (v) i out (ma) 17.0 16.5 16.0 15.5 15.0 14.5 ?3.3 ?3.6 ?3.9 ?4.2 ?4.7 ?5.0 01074-018 figure 18. i out vs. supply, v ee 200ps/div 200mv/div 1v ?1v 01074-019 95.55 rise 96.32 fall 20% proximal 80% distal figure 19. rise/fall times, v ee = ?3.3 v temperature ( c) propagtion delay (ps) 150 100 50 0 ?50 ?100 ?25 0 25 50 75 100 01074-020 figure 20. propagation delay, normalized at 25c vs. temperature rms pk-pk supply voltage (v cc , v ee ) jitter (ps) 100 80 60 40 20 0 3.0 3.5 4.0 4.5 5.0 01074-021 figure 21. jitter vs. supply 1.5 gbps, prbs 23 200ps/div 200mv/div 1v ?1v 01074-022 87.11 rise 87.36 fall 20% proximal 80% distal figure 22. rise/fall times, v ee = ?5 v
ad8150 rev. a | page 12 of 44 200ps/div 100mv/div 500mv ?500mv 01074-023 figure 23. eye pattern, v ee = ?3.3 v, 1.5 gbps prbs 23 100ps/div 100mv/div 500mv ?500mv 01074-025 figure 24. eye pattern, v ee = ?5 v, 1.5 gbps prbs 23
ad8150 rev. a | page 13 of 44 test circuit 01074-024 1.65k r l = 50 r l = 50 50 50 v cc v cc v tt 1.65k 105 hp8133a prbs generator tektronix 11801b sd22 sampling head ad8150 in out p n p n v ee v ee v tt v cc = 0v, v ee = ?3.3v or ?5v, v tt = ?1.6v r set = 1.54k , i out = 16ma, v oh = ?0.8v, v ol = ?1.8v intrinsic jitter of hp8133a and tektronix 11801b = 3ps rms, 17ps pk-pk figure 25. eye pattern test circuit
ad8150 rev. a | page 14 of 44 control interface control interface truth tables the following are truth tables for the control interface. table 4. basic control functions control pins reset cs we re update function 0 x x x x global reset. reset all second-rank enable bits to 0 (disable all outputs). 1 1 x x x control disable. ignore all logic (but the signal matrix still functions as programmed). d[6:0] are high impedance. 1 0 0 x x single output preprogram. write input configuration data from data bus d[6:0] into first rank of latches for the output selected by the output address bus a[4:0]. 1 0 x 0 x single output readback. readback in put configuration data from seco nd rank of latches onto data bus d[6:0] for the single output select ed by the output address bus a[4:0]. 1 0 x x 0 global update. copy input configuration data from all 17 first-rank latches into second rank of latches, updating signal matr ix connections for all outputs. 1 0 0 1 0 transparent write and update. it is possible to write da ta directly onto rank tw o. this simplifies logic when synchronous signal matrix updating is not necessary. table 5. address data examples output address pins msb to lsb enable bit input address pins msb to lsb a4 a3 a2 a1 a0 d6/e d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 x 0 0 0 0 0 0 lower address/data range. connect output 00 (a[4:0] = 00000) to input 00 (d[5:0] = 000000). 1 0 0 0 0 x 1 0 0 0 0 0 upper address/data range. connect output 16 (a[4:0] = 10000) to input 32 (d[5:0] = 100000). 1 enable output. connect selected output (a[4:0] = 0 to 16) to designated input (d[5:0] = 0 to 32) and enable output (d6 = 1). 0 x x x x x x disable output. di sable specified output (d6 = 0). 1 0 0 0 1 x broadcast connection. connect all 17 outputs to the same designated input and set all 17 enable bits to the value of d6. readback is not possible with the broadcast address. 1 0 0 1 0 x 1 0 0 0 0 1 reserved. any address or data co de greater or equal to these are reserved for future expansion or factory testing. 1 the binary output number may also be the broadcast connect ion designator, 10001x.
ad8150 rev. a | page 15 of 44 control interface timing diagrams 01074-026 a[4:0] inputs t csw t asw t wp t dsw t dhw t ahw t chw cs input we input d[6:0] inputs figure 26. first-rank write cycle table 6. first-rank write cycle symbol parameter conditions min typ max unit t csw setup time chip select to write enable t a = 25c 0 ns t asw address to write enable v dd = 5 v 0 ns t dsw data to write enable v cc = 5 v 15 ns t chw hold time chip select from write enable 0 ns t ahw address from write enable 0 ns t dhw data from write enable 0 ns t wp width of write enable pulse 15 ns
ad8150 rev. a | page 16 of 44 01074-027 cs input enabling out[0:16][n:p] outputs toggle out[0:16][n:p] outputs disabling out[0:16][n:p] outputs data from rank 1 previous rank 2 data data from rank 2 data from rank 1 update input t chu t uw t uot t uod t uoe t csu figure 27. second-rank update cycle table 7. second-rank update cycle symbol parameter conditions min typ max unit t csu setup time chip se lect to update t a = 25c 0 ns t chu hold time chip select from update v dd = 5 v 0 ns t uoe output enable times upda te to output enable v cc = 5 v 25 40 ns t uot output toggle times update to output reprogram 25 40 ns t uod output disable times update to output disabled 25 30 ns t uw width of update pulse 15 ns
ad8150 rev. a | page 17 of 44 01074-028 cs input enabling out[0:16][n:p] outputs input {data 2} input {data 1} input {data 1} input {data 0} disabling out[0:16][n:p] outputs update input we input t csu t uot t wot t wod t whu t chu t uoe t uw figure 28. first-rank write cycle and second-rank update cycle table 8. first-rank write cycle and second-rank update cycle symbol parameter conditions min typ max unit t csu setup time chip se lect to update t a = 25c 0 ns t chu hold time chip select from update v dd = 5 v 0 ns t uoe output enable times upda te to output enable v cc = 5 v 25 40 ns t woe 1 write enable to output enable 25 40 ns t uot output toggle times update to output reprogram 25 30 ns t wot write enable to output reprogram 25 30 ns t uod 1 output disable times update to output disabled 25 30 ns t wod write enable to output disabled 25 30 ns t whu setup time write enable to update 10 ns t uw width of update pulse 15 ns 1 not shown.
ad8150 rev. a | page 18 of 44 01074-029 d[6:0] outputs addr 1 addr 2 data {addr 1} data {addr 2} cs input re input a[4:0] inputs t csr t rde t aa t rha t chr t rdd figure 29. second-rank readback cycle table 9. second-rank readback cycle symbol parameter conditions min typ max unit t csr setup time chip select to read enable t a = 25c 0 ns t chr hold time chip select from read enable v dd = 5 v 0 ns t rha address from read enable v cc = 5 v 5 ns t rde enable time data from read enable 10 k 15 ns t aa access time data from address 20 pf on d[6:0] 15 ns t rdd release time data from read enable bus 15 30 ns
ad8150 rev. a | page 19 of 44 01074-030 reset input disabling out[0:16][n:p] outputs t tod t tw figure 30, asynchronous reset table 10. asynchronous reset symbol parameter conditions min typ max unit t tod disable time output disable from reset t a = 25c 25 30 ns t tw width of reset pulse v dd = 5 v 15 ns v cc = 5 v
ad8150 rev. a | page 20 of 44 control interface programming example the following conservative pattern connects all outputs to input 7, except output 16, which is connected to input 32. the vecto r clock period, t 0 , is 15 ns. it is possible to accelerate the execution of this pattern by deleting vectors 1, 4, 7, and 9. table 11. basic test pattern vector no. reset cs we re update a[4:0] d[6:0] comments 0 0 1 1 1 1 xxxxx xxxxxxx disable all outputs 1 1 1 1 1 1 xxxxx xxxxxxx 2 1 0 1 1 1 10001 1000111 all outputs to input 07 3 1 0 0 1 1 10001 1000111 write to first rank 4 1 0 1 1 1 10001 1000111 5 1 0 1 1 1 10000 1100000 output 16 to input 32 6 1 0 0 1 1 10000 1100000 write to first rank 7 1 0 1 1 1 10000 1100000 8 1 0 1 1 0 xxxxx xxxxxxx transfer to second rank 9 1 0 1 1 1 xxxxx xxxxxxx 10 1 1 1 1 1 xxxxx xxxxxxx disable interface 01074-031 update 7 0 1 2 16 33 1 of 17 decoders we d[0:6] a[0:4] rank 1 rank 2 17 rows of 7-bit latches reset 7 33 7 33 7 33 7 7 7 7 0 1 2 16 7 7 7 7 7 7 7 7 7 to 17 33 switch matrix 1 of 33 decoders re figure 31. control interface (simplified schematic)
ad8150 rev. a | page 21 of 44 control interface description the ad8150 control interface receives and stores the desired connection matrix for the 33 input and 17 output signal pairs. the interface consists of 17 rows of double-rank 7-bit latches, one row for each output. the 7-bit data-word stored in each of these latches indicates to which (if any) of the 33 inputs the output will be connected. one output at a time can be preprogrammed by addressing the output and writing the desired connection data into the first rank of latches. this process can be repeated until each of the desired output changes has been preprogrammed. all output connections can then be programmed at once by passing the data from the first rank of latches into the second rank. the output connections always reflect the data programmed into the second rank of latches and do not change until the first rank of data is passed into the second rank. if necessary for system verification, the data in the second rank of latches can be read back from the control interface. at any time, a reset pulse can be applied to the control interface to globally reset the appropriate second-rank data bits, disabling all 17 signal output pairs. this feature can be used to avoid output bus contention on system start-up. the contents of the first rank remain unchanged. the control interface pins are connected via logic-level translators. these translators allow programming and readback of the control interface using logic levels different from those in the signal matrix. to facilitate multiple chip address decoding, there is a chip- select pin. all logic signals except the reset pulse are ignored unless the chip-select pin is active. the chip-select pin disables only the control logic interface and does not change the operation of the signal matrix. the chip-select pin does not power down any of the latches, so any data programmed in the latches is preserved. all control pins are level-sensitive, not edge-triggered. control pin description a[4:0] inputs output address pins. the binary encoded address applied to these five input pins determines which one of the 17 outputs is being programmed (or being read back). the most significant bit is a4. d[6:0] inputs/outputs input configuration data pins. in write mode, the binary encoded data applied to pins d[6:0] determine which one of 33 inputs is to be connected to the output specified with the a[4:0] pins. the most significant bit is d5, and the least significant bit is d0. bit d6 is the enable bit, setting the specified output signal pair to an enabled state if d6 is logic high, or to a disabled state, high impedance, if d6 is logic low. in readback mode, pins d[6:0] are low impedance outputs, indicating the data-word stored in the second rank for the output specified with the a[4:0] pins. the readback drivers were designed to drive high impedances only, so external drivers connected to d[6:0] should be disabled during readback mode. we input first-rank write enable. forcing this pin to logic low allows the data on pins d[6:0] to be stored in the first-rank latch for the output specified by pins a[4:0]. the we pin must be returned to a logic high state after a write cycle to avoid overwriting the first-rank data. update input second-rank write enable. forcing this pin to logic low allows the data stored in all 17 first-rank latches to be transferred to the second-rank latches. the signal connection matrix will be reprogrammed when the second-rank data is changed. this is a global pin, transferring all 17 rows of data at once. it is not necessary to program the address pins. it should be noted that after initial power-up of the device, the first-rank data is undefined. it may be desirable to preprogram all seventeen outputs before performing the first update cycle.
ad8150 rev. a | page 22 of 44 re input second-rank read enable. forcing this pin to logic low enables the output drivers on the bidirectional d[6:0] pins, entering the readback mode of operation. by selecting an output address with the a[4:0] pins and forcing re to logic low, the 7-bit data stored in the second-rank latch for that output address will be written to the d[6:0] pins. data should not be written to the d[6:0] pins externally while in readback mode. the re and we pins are not exclusive and may be used at the same time, but data should not be written to the d[6:0] pins from external sources while in readback mode. cs input chip select. this pin must be forced to logic low to program or receive data from the logic interface, with the exception of the reset pin, described below. this pin has no effect on the signal pairs and does not alter any of the stored control data. reset input global output disable pin. forcing the reset pin to logic low will reset the enable bit, d6, in all 17 second-rank latches, regardless of the state of any other pins. this has the effect of immediately disabling the 17 output signal pairs in the matrix. it is useful to momentarily hold reset at a logic low state when powering up the ad8150 in a system that has multiple output signal pairs connected together. failure to do this may result in several signal outputs contending after power-up. the reset pin is not gated by the state of the chip-select pin, cs . it should be noted that the reset pin does not program the first rank, which will contain undefined data after power-up. control interface translators the ad8150 control interface has two supply pins, v dd and v ss . the potential between the positive logic supply v dd and the negative logic supply v ss must be at least 3 v and no more than 5 v. regardless of supply, the logic threshold is approximately 1.6 v above v ss , allowing the interface to be used with most cmos and ttl logic drivers. the signal matrix supplies, v cc and v ee , can be set independent of the voltage on v dd and v ss , with the constraints that (v dd ? v ee ) 10 v. these constraints will allow operation of the control interface on 3 v or 5 v while the signal matrix is operated on 3.3 v or 5 v pecl, or on ?3.3 v or ?5 v ecl.
ad8150 rev. a | page 23 of 44 circuit description the ad8150 is a high speed 33 17 differential crosspoint switch designed for data rates up to 1.5 gbps per channel. the ad8150 supports pecl-compatible input and output levels when operated from a 5 v supply (v cc = 5 v, v ee = gnd) or ecl-compatible levels when operated from a ?5 v supply (v cc = gnd, v ee = ?5 v). to save power, the ad8150 can run from a 3.3 v supply to interface with low voltage pecl circuits or a ?3.3 v supply to interface with low voltage ecl circuits. the ad8150 utilizes differential current-mode outputs with individual disable control, which facilitates busing together the outputs of multiple ad8150s to assemble larger switch arrays. this feature also reduces the system to assemble larger switch arrays, reduces system crosstalk, and can greatly reduce power dissipation in a large switch array. a single external resistor programs the current for all enabled output stages, allowing for user control over output levels with different output termination schemes and transmission line characteristic impedances. high speed data inputs (inxxp, inxxn) the ad8150 has 33 pairs of differential voltage-mode inputs. the common-mode input range extends from the positive supply voltage (v cc ) down to include standard ecl or pecl input levels (v cc ? 2 v). the minimum differential input voltage is less than 300 mv. unused inputs may be connected directly to any level within the allowed common-mode input range. a simplified schematic of the input circuit is shown in figure 32. 01074-032 v cc v ee inxxp inxxn figure 32. simplified input circuit to maintain signal fidelity at the high data rates supported by the ad8150, the input transmission lines should be terminated as close to the input pins as possible. the preferred input termination structure will depend primarily on the application and the output circuit of the data source. standard ecl components have open emitter outputs that require pull-down resistors. three input termination networks suitable for this type of source are shown in figure 33. the characteristic impedance of the transmission line is shown as z o . the resistors, r1 and r2, in the thevenin termination are chosen to synthesize a v tt source with an output resistance of z o and an open-circuit output voltage equal to v cc ? 2 v. the load resistors (r l ) in the differential termination scheme are needed to bias the emitter followers of the ecl source. 01074-033 (b) inxxp inxxn z o z o r2 r2 r1 r1 ecl source v cc v cc ? 2v v ee (a) inxxp inxxn ecl source v cc v tt = vcg2v z o z o z o z o (c) inxxp inxxn ecl source v cc v ee r l r l z o z o 2z o figure 33. ad8150 input termination from ecl/pecl sources: a) parallel termination using v tt supply; b) thevenin equivalent termination; and c) differential termination if the ad8150 is driven from a current-mode output stage such as another ad8150, the input termination should be chosen to accommodate that type of source, as explained in the following section. high speed data outputs (outyyp, outyyn) the ad8150 has 17 pairs of differential current-mode outputs. the output circuit, shown in figure 34, is an open-collector npn current switch with resistor-programmable tail current and output compliance extending from the positive supply voltage (v cc ) down to standard ecl or pecl output levels (v cc ? 2 v). the outputs may be disabled individually to permit outputs from multiple ad8150s to be connected directly. since the output currents of multiple enabled output stages connected in this way sum, care should be taken to ensure that the output compliance limit is not exceeded at any time; this can be achieved by disabling the active output driver before enabling an inactive driver.
ad8150 rev. a | page 24 of 44 01074-034 v cc v ee v cc ? 2v i out v ee disable outyyp outyyn figure 34. simplified output circuit to ensure proper operation, all outputs (including unused output) must be pulled high, using external pull-up networks, to a level within the output compliance range. if outputs from multiple ad8150s are wired together, a single pull-up network may be used for each output bus. the pull-up network should be chosen to keep the output voltage levels within the output compliance range at all times. recommended pull-up networks to produce pecl/ecl 100k- and 10k-compatible outputs are shown in figure 35. alternatively, a separate supply can be used to provide v com , making r com and d com unnecessary. 01074-035 outyyn outyyp ad8150 outyyn outyyp ad8150 v cc r l r l r l v cc r l v com r com v com d com figure 35. output pull-up networks: a) ecl 100k, b) ecl 10k the output levels are simply: () () () mode d v v v mode r i v v r i v v v r i v v v v com cc com com out cc com l out ol oh swing l out com ol com oh k 10 k 100 ? = ? = = ? = ? = = the common-mode adjustment element (r com or d com ) may be omitted if the input range of the receiver includes the positive supply voltage. the bypass capacitors reduce common-mode perturbations by providing an ac short from the common nodes (v com ) to ground. when busing together the outputs of multiple ad8150s or when running at high data rates, double termination of its outputs is recommended to mitigate the impact of reflections due to open transmission line stubs and the lumped capacitance of the ad8150 output pins. a possible connection is shown in figure 36; the bypass capacitors provide an ac short from the common nodes of the termination resistors to ground. to maintain signal fidelity at high data rates, the stubs connecting the output pins to the output transmission lines or load resistors should be as short as possible. 01074-036 r l r l r l r l z o z o z o z o v cc r com v com outyyn outyyp ad8150 outyyn outyyp ad8150 receiver figure 36. double termination of ad8150 outputs in this case, the output levels are: ( ) () () l out ol oh swing l out com ol l out com oh r i v v v r i v v r i v v 2 1 4 3 4 1 = ? = ? = ? = output current set pin (ref) a simplified schematic of the reference circuit is shown in figure 37. a single external resistor connected between the ref pin and v ee determines the output current for all output stages. this feature allows a choice of pull-up networks and transmission line characteristic impedances while still achieving a nominal output swing of 800 mv. at low data rates, substantial power savings can be achieved by using lower output swings and higher load resistances. 01074-037 r set v ee v cc i out /25 ad8150 ref 1.25v figure 37. simplified reference circuit
ad8150 rev. a | page 25 of 44 the resistor value current is given by the following expression: out set i r 25 = example: ma 2 . 16 k 54 . 1 = = out set i for r the minimum set resistor is r set,min = 1 k, resulting in i out,max = 25 ma. the maximum set resistor is r set,max = 5 k, resulting in i out,min = 5 ma. nominal 800 mv output swings can be achieved in a 50 load using r set = 1.56 k (i out = 16.2 ma) or in a doubly terminated 75 load using r set = 1.17 k (i out = 21.3 ma). to minimize stray capacitance and avoid the pickup of unwanted signals, the external set resistor should be located close to the ref pin. bypassing the set resistor is not recommended. power supplies there are several options for the power supply voltages for the ad8150, because there are two separate sections of the chip that require power supplies. these are the control logic and the high speed data paths. the voltage levels of these supplies can vary, depending on the system architecture. logic supplies the control (programming) logic is cmos and is designed to interface with any of the various standard single-ended logic families (cmos or ttl). its supply voltage pins are v dd (pin 170, logic positive) and v ss (pin 152, logic ground). in all cases the logic ground should be connected to the system digital ground. v dd should be supplied at a voltage between 3.3 v and 5 v to match the supply voltage of the logic family that is used to drive the logic inputs. v dd should be bypassed to ground with a 0.1 f ceramic capacitor. the absolute maximum voltage from v dd to v ss is 5.5 v. data path supplies the data path supplies have more options for their voltage levels. the choices here will affect several other areas, such as power dissipation, bypassing, and common-mode levels of the inputs and outputs. the more positive voltage supply for the data paths is v cc (pins 41, 98, 149, and 171). the more negative supply is v ee , which appears on many pins that will not be listed here. the maximum allowable voltage across these supplies is 5.5 v. the first choice in the data path power supplies is to decide whether to run the device as ecl (emitter-coupled logic) or pecl (positive ecl). for ecl operation, v cc will be at ground potential, and v ee will be at a negative supply between ?3.3 v and ?5 v. this will make the common-mode voltage of the inputs and outputs a negative voltage (see figure 38). 01074-038 v cc v dd v ee v ss data paths control logic 3v to 5v 3v to 5v gnd gnd 0.1 f 0.1 f (one for every two v ee pins) ad8150 figure 38. power supplies and bypassing for ecl operation if the data paths are to be dc-coupled to other ecl logic devices that run with ground as the most positive supply and a negative voltage for v ee , then this is the proper way to run. however, if the part is to be ac coupled, it is not necessary to have the input/output common mode at the same level as the other system circuits, but it will probably be more convenient to use the same supply rails for all devices. for pecl operation, v ee will be at ground potential, and v cc will be a positive voltage from 3.3 v to 5 v. thus, the common mode of the inputs and outputs will be at a positive voltage. these can then be dc coupled to other pecl operated devices. if the data paths are ac coupled, then the common-mode levels do not matter, see figure 39. 01074-039 data paths control logic v cc v dd v ee v ss 0.1 f 0.1 f (one for each v cc pin, 4 required) 3v to 5v 3v to 5v gnd gnd ad8150 figure 39. power supplies and bypassing for pecl operation
ad8150 rev. a | page 26 of 44 184 183 182 181 180 179 178 177 176 175 174 173 171 170 169 168 167 166 165 164 163 162 172 161 160 159 157 156 155 154 153 152 158 151 150 149 147 146 145 144 143 142 141 140 139 148 59 60 61 62 63 64 65 66 67 68 47 48 49 50 51 52 53 54 55 56 57 58 69 70 71 72 74 75 76 77 78 73 79 80 81 82 84 85 86 87 83 88 89 90 91 92 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 40 39 38 37 41 43 42 45 44 46 in20p v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v cc in20n in21p in21n in22p in22n in23p in23n in24p in24n in25p in25n in26p in26n in27p in27n in28p in28n in29p in29n in30p in30n in31p in31n in32p in32n out16n out16p v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v cc v ee in12n in12p in11n in11p in10n in10p in09n in09p in08n in08p in07n in07p in06n in06p in05n in05p in04n in04p in03n in03p in02n in02p in01n in01p in00n in00p out00p out00n 122 137 138 132 133 134 135 130 131 129 136 127 128 123 124 125 126 120 121 118 119 116 117 113 114 115 111 112 109 110 108 105 106 107 104 102 103 100 101 95 96 97 98 99 93 94 pin 1 indicator ad8150 184l lqfp top view (not to scale) in19n in19p in18n in18p in17n in17p in16n in16p reset cs re we update a0 a1 a2 a3 a4 d0 d1 d2 d3 d4 d5 d6 in15n in15p in14n in14p in13n in13p v ee v ee v ee v ee v ee v ss v cc v ee v cc v ee v ee v ee v cc v dd out15n out15p out14n out14p out13n out13p out12n out12p out11n out11p out10n out10p out09n out09p out08n out08p out07n out07p out06n out06p out05n out05p out04n out04p out03n out03p out02n out02p out01n out01p v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee 01074-050 v cc c31 0.01 f v cc c32 0.01 f v cc c29 0.01 f v cc c4 0.01 f v cc c5 0.01 f v ee c12 0.01 f v dd c14 0.01 f v cc c6 0.01 f v cc c7 0.01 f v ee c13 0.01 f v cc c30 0.01 f v cc c10 0.01 f v ee c9 0.01 f v cc c8 0.01 f c11 0.01 f v ee c60 0.01 f c15 0.01 f r203 1.5k figure 40. bypassing schematic
ad8150 rev. a | page 27 of 44 power dissipation for analysis, the power dissipation of the ad8150 can be divided into three separate parts. these are the control logic, the data path circuits, and the (ecl or pecl) outputs, which are part of the data path circuits, but can be dealt with separately. the first of these, the control logic, is cmos technology and does not dissipate a significant amount of power. this power will, of course, be greater when the logic supply is 5 v than when it is 3 v, but overall it is not a significant amount of power and can be ignored for thermal analysis. 01074-040 data paths control logic v cc v dd v ee i out r out v out low ? v ee v ss gnd gnd ad8150 i, data path logic figure 41. major power consumption paths the data path circuits operate between the supplies v cc and v ee . as described in the power supply section, this voltage can range from 3.3 v to 5 v. the current consumed by this section will be constant, so operating at a lower voltage can save about 40 percent in power dissipation. the power dissipated in the data path outputs is affected by several factors. the first is whether the outputs are enabled or disabled. the worst case occurs when all of the outputs are enabled. the current consumed by the data path logic can be approximated by () [ ] () enabled outputs of i i out cc # ma 3 ma 20 ma 5 . 4 ma 30 + + = this says that there will always be a minimum of 30 ma flowing. i cc will increase by a factor that is proportional to both the number of enabled outputs and the programmed output current. the power dissipated in this circuit section will simply be the voltage of this section (v cc ? v ee ) times the current. for a worst case, assume that v cc ? v ee is 5.0 v, all outputs are enabled and the programmed output current is 25 ma. the power dissipated by the data path logic will be () [] { } mw 826 17 ma 3 ma 20 ma 25 ma 5 . 4 ma 25 v 0 . 5 = + + = p the power dissipated by the output current depends on several factors. these are the programmed output current, the voltage drop from a logic low output to v ee , and the number of enabled outputs. a simplifying assumption is that one of each (enabled) differential output pair will be low and draw the full output current (and dissipate most of the power for that output), while the complementary output of the pair will be high and draw insignificant current. thus, the power dissipation of the high output can be ignored, and the output power dissipation for each output can be assumed to occur in a single static low output that sinks the full output-programmed current. the voltage across which this current flows can also vary, depending on the output circuit design and the supplies that are used for the data path circuitry. in general, however, there will be a voltage difference between a logic low signal and v ee . this is the drop across which the output current flows. for a worst case, this voltage can be as high as 3.5 v. thus, for all outputs enabled and the programmed output current set to 25 ma, the power dissipated by the outputs is ( ) w 49 . 1 17 ma 25 v 5 . 3 = = p
ad8150 rev. a | page 28 of 44 heat sinking depending on several factors in its operation, the ad8150 can dissipate 2 w or more. the part is designed to operate without the need for an explicit external heat sink. however, the package design offers enhanced heat removal via some of the package pins to the pc board traces. the v ee pins on the input sides of the package (pins 1 to 46 and pins 93 to 138) have finger extensions inside the package that connect to the paddle on which the ic chip is mounted. these pins provide a lower thermal resistance from the ic to the v ee pins than pins that just have a bond wire. as a result, these pins can be used to enhance the heat removal process from the ic to the circuit board and ultimately to the ambient. the v ee pins described above should be connected to a large area of circuit board trace material to take the most advantage of their lower thermal resistance. if there is a large area available on an inner layer that is at v ee potential, then vias can be provided from the package pin traces to this layer. there should be no thermal-relief pattern when connecting the vias to the inner layers for these v ee pins. additional vias in parallel and close to the pin leads can provide an even lower thermal resistive path. if possible to use, 2 oz. copper foil will provide better heat removal than 1 oz. the ad8150 package has a specified thermal impedance, ja , of 30c/w. this is the worst case still-air value that can be expected when the circuit board does not significantly enhance the heat removal from the package. by using the concept described above or by using forced-air circulation, the thermal impedance can be lowered. for an extreme worst case analysis, the junction rise above the ambient can be calculated assuming 2 w of power dissipation and ja of 30c/w to yield a 60c rise above the ambient. there are many techniques described above that can mitigate this situation. most actual circuits will not result in such a high rise of the junction temperature above the ambient.
ad8150 rev. a | page 29 of 44 applications ad8150 input and output busing although the ad8150 is a digital part, in any application that runs at high speed, analog design details will have to be given very careful consideration. at high data rates, the design of the signal channels will have a strong influence on the data integrity and its associated jitter and ultimately bit error rate (ber). while it might be considered very helpful to have a suggested circuit board layout for any particular system configuration, this is not something that can be practically realized. systems come in all shapes, sizes, speeds, performance criteria, and cost constraints. therefore, some general design guidelines will be presented that can be used for all systems and judiciously modified where appropriate. high speed signals travel best, that is, maintain their integrity, when they are carried by a uniform transmission line that is properly terminated at either end. any abrupt mismatches in impedance or improper termination will create reflections that will add to or subtract from parts of the desired signal. small amounts of this effect are unavoidable, but too much will distort the signal to the point that the channel ber will increase. it is difficult to fully quantify these effects because they are influenced by many factors in the overall system design. a constant-impedance transmission line is characterized by having a uniform cross-sectional profile over its entire length. in particular, there should be no stubs, which are branches that intersect the main run of the transmission line. these can have an electrical appearance that is approximated by a lumped element, such as a capacitor, or if long enough, as another transmission line. to the extent that stubs are unavoidable in a design, their effect can be minimized by making them as short as possible and as high an impedance as possible. figure 36 shows a differential transmission line that connects two differential outputs from ad8150s to a generic receiver. a more generalized system can have more outputs bused and more receivers on the same bus, but the same concepts apply. the inputs of the ad8150 can also be considered a receiver. the transmission lines that bus all of the devices together are shown with terminations at each end. the individual outputs of the ad8150 are stubs that intersect the main transmission line. ideally, their current-source outputs would be infinite impedance, and they would have no effect on signals that propagate along the transmission line. in reality, each external pin of the ad8150 projects into the package and has a bond wire connected to the chip inside. on-chip wiring then connects to the collectors of the output transistors and to esd protection diodes. unlike some other high speed digital components, the ad8150 does not have on-chip terminations. while the location of such terminations would be closer to the actual end of the transmission line for some architectures, this concept can limit system design options. in particular, it is not possible to bus more than two inputs or outputs on the same transmission line and it is not possible to change the value of these terminations to use them for different impedance transmission lines. the ad8150, with the added ability to disable its outputs, is much more versatile in these types of architectures. if the external traces are kept to a bare minimum, the output will present a mostly lumped capacitive load of about 2 pf. a single stub of 2 pf will not seriously adversely affect signal integrity for most transmission lines, but the more of these stubs, the more adverse their influence will be. one way to mitigate this effect is to locally reduce the capacitance of the main transmission line near the point of stub intersection. some practical means for doing this are to narrow the pc board traces in the region of the stub and/or to remove some of the ground plane(s) near this intersection. the effect of these techniques will locally lower the capacitance of the main transmission line at these points, while the added capacitance of the ad8150 outputs will compensate for this reduction in capacitance. the overall intent is to create as uniform a transmission line as possible. in selecting the location of the termination resistors, it is important to keep in mind that, as their name implies, they should be placed at either end of the line. there should be no, or minimal, projection of the transmission line beyond the point where the termination resistors connect to it.
ad8150 rev. a | page 30 of 44 evaluation board an evaluation board has been designed and is available to rapidly test the main features of the ad8150. this board lets the user analyze the analog performance of the ad8150 channels and easily control the configuration of the board by a standard pc. differential inputs and outputs provide the interface for all channels with the connections made by a 50 smb-type connector. this type of connector was chosen for its rapid mating and unmating action. the use of smb-type connectors minimizes the size and minimizes the effort of rearranging interconnects that would be required if using sma-type connectors. configuration programming the board is configurable by one of two methods. for ease of use, custom software is provided that controls the ad8150 programming via the parallel port of a pc. this requires a user- supplied standard printer cable that has a db-25 connector at one end (parallel- or printer-port interface) and a centronix- type connector at the other that connects to p2 of the ad8150 evaluation board. the programming with this scheme is done in a serial fashion, so it is not the fastest way to configure the ad8150 matrix. however, the user interface makes it very convenient to use this programming method. if a high speed programming interface is desired, the ad8150 address and data buses are directly available on p3. the source of the program signals can be a piece of test equipment, such as the tektronix hfs-9000 digital test generator, or some other user-supplied hardware that generates programming signals. when using the pc interface, the jumper at w1 should be installed and no connections should be made to p3. when using the p3 interface, no jumper is installed at w1. there are locations for termination resistors for the address and data signals if these are necessary. power supplies the ad8150 is designed to work with standard ecl logic levels. this means that v cc is at ground and v ee is at a negative supply. the shells of the i/o smb connectors are at v cc potential. thus, when operating in the standard ecl configuration, test equipment can be directly connected to the board, because the test equipment will also have its connector shells at ground potential. operating in pecl mode requires v cc to be at a positive voltage while v ee is at ground. since this would make the shells of the i/o connectors at a positive voltage, it can cause problems when directly connecting to test equipment. some equipment, such as battery operated oscilloscopes, can be floated from ground, but care should be taken with line-powered equipment so that a dangerous situation is not created. refer to the test equipments manual. the voltage difference from v cc to v ee can range from 3 v to 5 v. power savings can be realized by operating at a lower voltage without any compromise in performance. a separate connection is provided for v tt , the termination potential of the outputs. this can be at a voltage as high as v cc , but power savings can be realized if v tt is at a voltage that is somewhat lower. please consult elsewhere in the data sheet for the specification for the limits of the v tt supply. as a practical matter, current on the evaluation board will flow from the v tt supply through the termination resistors and then through the ad8150 from its outputs to the v ee supply. when running in ecl mode, v tt will want to be at a negative supply. most power supplies will not allow their ground to connect to v cc and will not allow their negative supply to connect to v tt . this will require them to source current from their negative supply, which will not return to the ground terminal. thus, v tt should be referenced to v ee when running in ecl mode, or a true bipolar supply should be used. the digital supply is provided to the ad8150 by the v dd and v ss pins. v ss should always be at ground potential to make it compatible with standard cmos or ttl logic. v dd can range from 3 v to 5 v and should be matched to the supply voltage of the logic used to control the ad8150. however, since pcs use 5 v logic on their parallel port, v dd should be at 5 v when using a pc to program the ad8150. software installation the software to operate the ad8150 is provided on two 3.5" floppy disks. the software is installed by inserting disk 1 into the floppy drive of a pc and running the setup.exe program. this will routinely install the software and prompt the user to change to disk 2. the setup program will also prompt the user to select the directory location to store the program. after running the software, the user will be prompted to identify which (of three) software driver is used with the pcs parallel port. the default is lpt1, which is most commonly used. however, some laptops commonly use the prn driver. it is also possible that some systems are configured with the lpt2 driver. if it is not known which driver is used, it is best to select lpt1 and proceed to the next screen. this will show a full array of buttons that allows the connection of any input to output of the ad8150. all of the outputs should be in the output off state immediately after the program starts running. any of the active buttons can be selected with a mouse click, which will send out one burst of programming data.
ad8150 rev. a | page 31 of 44 after this, the pc keyboards left or right arrow key can be held down to generate a steady stream of programming signals out of the parallel port. the clock test point on the ad8150 evaluation board can be monitored with an oscilloscope for any activity (a user-supplied printer cable must be connected). if there is a square wave present, then the proper software driver is selected for the pcs parallel port. if there is no signal present, then another driver should be tried by selecting the parallel port menu item from the file pull- down menu selection under the title bar. select a different software driver and carry out the above test until signal activity is present at the clock test point. software operation any button can be clicked in the matrix to program the input- to-output connection. this will send the proper programming sequence out of the pc parallel port. since only one input can be programmed to a given output at a time, clicking a button in a horizontal row will cancel previous selections in that row. however, any number of outputs can share the same input. refer to figure 42. a shortcut for programming all outputs to the same input is to use the broadcast feature. after clicking on the broadcast connection button, a window will appear that will prompt the user to select which input should be connected to all outputs. the user should type in an integer from 0 to 32 and then click ok. this will send out the proper program data and return to the main screen with a full column of buttons selected under the chosen input. the off column can be used to disable whichever output one chooses. to disable all outputs, click the global reset button. this will select the full column of off buttons. two scratchpad memories (memory 1 and memory 2) are provided to conveniently save a particular configuration. however, these registers are erased when the program is terminated. for long-term storage of configurations, the disks storage memory should be used. the save and load selections can be accessed from the file pull-down menu under the title bar. 01074-041 figure 42. evaluation board controller
ad8150 rev. a | page 32 of 44 pcb layout 01074-042 figure 43. component side
ad8150 rev. a | page 33 of 44 01074-043 figure 44. circuit side
ad8150 rev. a | page 34 of 44 01074-044 figure 45. silkscreen top
ad8150 rev. a | page 35 of 44 01074-045 figure 46. solder mask top
ad8150 rev. a | page 36 of 44 01074-046 figure 47. silkscreen bottom
ad8150 rev. a | page 37 of 44 01074-047 figure 48. solder mask bottom
ad8150 rev. a | page 38 of 44 01074-048 figure 49. int1 (v ee )
ad8150 rev. a | page 39 of 44 01074-049 figure 50. int2 (v cc )
ad8150 rev. a | page 40 of 44 p52 p53 r93 in24p in24n r94 r92 p16 p17 r39 in06p in06n r40 r38 v cc v ee v ee v ee v ee v ee v ee v ee v cc v cc v cc v cc v cc v cc p4 p5 r20 in00p in00n r19 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k r21 p18 p19 r42 in07p in07n r41 r43 v cc v ee v ee v cc p6 p7 r24 in01p in01n r25 105 1.65k 1.65k 105 1.65k 1.65k r23 v cc v ee v ee v ee v ee v ee v ee v ee v cc v cc v cc v cc v cc v cc v cc v ee v ee v ee v ee v ee v ee v cc v cc v cc v cc v cc p28 p29 r57 in12p in12n r58 r56 p40 p41 r90 in18p in18n r89 r91 p54 p55 r96 in25p in25n r95 r97 v ee v ee v cc v cc 105 1.65k 1.65k 105 1.65k 1.65k p42 p43 r87 in19p in19n r88 r86 p64 p65 r117 in30p in30n r116 r118 v ee v cc 105 1.65k 1.65k p66 p67 r114 in31p in31n r115 r113 p56 p57 r99 in26p in26n r98 r100 p20 p21 r45 in08p in08n r44 r46 p8 p9 r27 in02p in02n r28 r26 p32 p33 r63 in14p in14n r62 r64 p44 p45 r84 in20p in20n r85 r83 p68 p69 r111 in32p in32n r112 r110 p60 p61 r105 in28p in28n r104 r106 p24 p25 r51 in10p in10n r50 r52 p12 p13 r33 in04p in04n r34 r32 p36 p37 r69 in16p in16n r68 r70 p48 p49 r78 in22p in22n r79 r77 p30 p31 r60 in13p in13n r59 r61 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k v cc v ee v ee v cc p22 p23 r48 in09p in09n r47 r49 p10 p11 r30 in03p in03n r31 r29 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k v ee v ee v cc v cc p58 p59 r102 in27p in27n r101 r103 p46 p47 r81 in21p in21n r82 r80 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k v cc v ee v ee v cc p26 p27 r54 in11p in11n r53 r55 p14 p15 r36 in05p in05n r37 r35 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k v ee v ee v cc v cc p62 p63 r108 in29p in29n r107 r109 p50 p51 r75 in23p in23n r76 r74 105 1.65k 1.65k 105 1.65k 1.65k 105 1.65k 1.65k p34 p35 r66 in15p in15n r65 r67 p38 p39 r72 in17p in17n r71 r73 p103 p102 r121 out00n r122 out00p p87 r160 out08n r162 v tt v tt 49.9 49.9 49.9 49.9 v tt v tt 49.9 49.9 49.9 49.9 v tt v tt 49.9 49.9 49.9 49.9 v tt v tt 49.9 49.9 49.9 49.9 v tt v tt 49.9 49.9 49.9 49.9 v tt v tt 49.9 49.9 49.9 49.9 v tt v tt 49.9 49.9 49.9 49.9 v tt v tt 49.9 49.9 49.9 49.9 p86 out08p v cc v tt c16 0.01 f 0.01 f 0.01 f v cc v tt c82 v cc v tt c83 p71 r200 49.9 out16n r198 49.9 p70 out16p v tt out15n out15p r190 r192 out07n out07p r155 r153 p91 r150 out06n r152 p90 out06p p75 r195 out14n r193 p74 out14p p89 p88 p73 p72 p93 p92 p77 p76 p97 p96 p81 p80 p101 p100 p85 p84 r180 out13n r182 out13p r145 out05n r143 out05p p95 r140 out04n r142 p94 out04p p79 r185 out12n r183 p78 out12p r170 out11n r172 out11p r135 out03n r133 out03p p99 r130 out02n r132 p98 out02p p83 r175 out10n r173 p82 out10p r165 out09n r163 out09p r125 out01n r127 out01p 01074-051 figure 51. input/output connections and bypassing
ad8150 rev. a | page 41 of 44 + p1 6 p1 1 p1 2 p1 3 p1 4 p1 7 p1 5 + + c2 10 f c1 10 f c3 10 f p104 p105 out_en d0 d1 d2 d3 d4 d5 d6 d7 1 2 3 4 5 6 7 8 9 gnd 10 q0 q1 q2 q3 q4 q5 q6 q7 20 19 18 17 16 15 14 13 12 clk 11 read p2 7 reset p2 3 write p2 8 update p2 4 chip_select p2 2 write p3 13 reset p3 7 read p3 11 d0 p3 27 a4 p3 25 a3 p3 23 a2 p3 21 a1 p3 19 a0 p3 17 d6 p3 39 d5 p3 37 d4 p3 35 d3 p3 33 d2 d1 p3 29 update p3 15 chip_select p3 9 v dd p3 5 v ss v dd v ss v ss v ss v ss v ss v ss p3 14 p3 8 p3 12 p3 28 p3 26 p3 24 p3 22 p3 20 p3 18 p3 40 p3 38 p3 36 a2 data p2 5 clk p2 6 clk data p2 25 r7 49 r8 49 r9 49 r10 49 r11 49 r12 49 r13 49 r14 49 r15 49 r16 49 r17 49 r18 49 r1 20k out_en d0 d1 d2 d3 d4 d5 d6 d7 1 2 3 4 5 6 7 8 9 gnd 10 q0 q1 q2 q3 q4 q5 q6 q7 20 19 18 17 16 15 14 13 12 clk 11 p3 31 a4 p3 34 p3 32 p3 30 p3 16 p3 10 p3 6 a3 tp5 tp4 tp6 tp7 tp8 chip_select 168 update 165 write 166 reset 169 read 167 a4 74hc132 74hc132 1 2 4 5 w1 74hc14 a1 74hc14 a1 74hc14 a1 1 2 3 4 5 6 74hc74 74hc74 160a4 161a3 162a2 163a1 164a0 tp9 tp10 tp11 tp12 tp13 tp20 tp14 tp15 tp16 tp17 tp18 tp19 153d6 154d5 155d4 156d3 157d2 158d1 159d0 3 6 v ss v ss v dd v ss v ss v ss v ss v ss v ss v dd v ss v dd v cc v cc 9 10 8 a4 a1 11 10 a1 13 12 12 13 11 a4 74hc14 a1 9 8 74hc14 74hc14 74hc132 74hc132 v dd v tt v cc v tt v tt v cc v cc v ee v ee v dd v ss a1, 4 pin 14 is tied to v dd . a1, 4 pin 7 is tied to v ss . c86 0.1 f c87 0.1 f c88 0.1 f c89 0.1 f v ss v dd v ss v dd v ss v dd v ss v dd v ee v dd v ss v dd v ss v ss v ss v ss v ss v ss v ss v ss r2 49k r3 49k r4 49k r5 49k r6 49k 01074-052 v cc v ee j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 j13 j14 j15 j16 j17 j18 j19 j20 j21 j22 j23 j24 j25 v cc v ee j26 j27 j28 j29 j30 j31 j32 j33 j34 j35 j36 j37 j38 j39 j40 j41 j42 j43 j44 j45 j46 j47 j48 j49 j50 figure 52. control logic and bypassing
ad8150 rev. a | page 42 of 44 outline dimensions 139 138 47 46 92 93 184 top view (pins down) 1 0.40 bsc lead pitch 0.23 0.18 0.13 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 22.20 22.00 sq 21.80 20.20 20.00 sq 19.80 figure 53. 184-lead low profile quad flat package [lqfp] (st-184) dimensions shown in millimeters ordering guide 1 model temperature range package description package option ad8150ast 0c to 85c 184-lead low profil e quad flat package [lqfp] st-184 ad8150astz 2 0c to 85c 184-lead low profile quad flat package [lqfp] st-184 ad8150-eval evaluation board 1 details of lead finish composition can be found on the adi website at www.analog.com by reviewing the material descri ption of each relevant package. 2 z = pb-free part.
ad8150 rev. a | page 43 of 44 notes
ad8150 rev. a | page 44 of 44 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c01074C0C9/05(a)

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